The invention generally relates to a semiconductor device and method of forming the same, and more particularly to a device and method that improves operating characteristics by forming a transistor in upper silicon of a SOI (silicon-on-insulator) wafer, that is, in an active region of a second silicon layer, wherein a silicide layer is formed at an interface of the active region and a device isolation region.
As the length of a gate electrode of a semiconductor device is reduced to below 0.15 xcexcm, the channel resistance of the device is reduced, which relatively increases the importance of the parasitic resistance during device operation. Due to this phenomenon, salicide technology is required to reduce contact resistance between a gate and a diffusion layer in a high speed logic device.
In addition, because increasing the integration level of a device requires increasing wiring using a diffusion layer, reduction in the resistance of the diffusion layer and the gate electrode is required. However, the diffusion layer becomes shallower due to a decrease in the width of the gate electrode. Thus, the thickness of salicide is reduced, which undesirably increases the resistance of the diffusion layer.
Accordingly it is desirable to lower the resistance of the diffusion layer while solving the problem of a shallow junction using a SOI wafer in highly integrated semiconductor devices.
One solution is to use cobalt salicide, which has no dependency on the line width. However, this may result in leakage current. Leakage current is generated by lateral growth of salicide during formation of thick salicide in a depletion region at the edge of the field oxide and by diffusion of high melting metal used as silicide during the process of forming thick salicide.
The present invention provides a semiconductor device and method of forming the same that allows high integration of the device by forming a suicide layer at the interface of a device isolation film, which defines an active region in a second silicon layer of a SOI wafer and a second silicon layer of the active region.
The present invention provides a semiconductor device comprising a SOI wafer having a stacked structure of a first silicon layer, a buried insulating film and a second silicon layer; a trench formed by removing a predetermined region of the second silicon layer; a first silicide layer formed at the side walls of the trench; a device isolation film defining an active region of the SOI wafer formed by filling the trench; a gate electrode having a gate insulation film formed on the active region of the SOI wafer; an insulation spacer formed at the side walls of the gate electrode; impurity junction regions formed at both sides of the gate electrode in the active region of the SOI wafer; and a second silicide layer formed on the gate electrode and the impurity regions, wherein the first and the second silicide layers are comprised of a metal selected from the group consisting of titanium, cobalt, nickel, and tungsten.
The present invention also provides a method of forming a semiconductor device comprising forming a pad insulating film on a SOI wafer having a stacked structure of a first silicon layer, a buried insulating film, and a second silicon layer; etching a predetermined region of the pad insulating film and the second silicon layer by a lithography process using a device isolation mask to form a trench exposing the buried insulating film; forming a first silicide layer at side walls of the trench; forming a device isolation film defining an active region by filling the trench; forming a transistor having a gate electrode, a insulation spacer and impurity junction regions on the second silicon layer in the active region; and forming a second silicide layer on the gate electrode and the impurity junction regions.
A first silicide layer is formed by forming a high melting point metal layer on the entire surface having a thickness in a range of 100-300 xc3x85 using a CVD method, performing an annealing process, and removing an unreacted portion of the high melting point metal layer, wherein the high melting point metal layer comprises a metal selected from the group consisting of titanium, cobalt, nickel, and tungsten. The annealing process is performed at a temperature in a range of 900-1000xc2x0 C. for 10-60 seconds, and the unreacted portion of the high melting point metal layer is removed by performing a first wet etch process using a HNO3 solution and a second wet etch process using a HF solution diluted in the HNO3 solution. A second silicide layer is formed by forming a high melting point metal layer having a predetermined thickness on the entire surface, performing a first annealing process at a temperature in a range of 650-750xc2x0 C. for 10-30 seconds, removing an unreacted portion of the high melting point metal layer, and performing a second annealing process at a temperature in a range of 800-1000xc2x0 C. for 10-30 seconds, wherein the high melting point metal layer comprises a metal selected from the group consisting of titanium, cobalt, nickel, and tungsten.
In accordance with the present invention, a transistor having an improved operating characteristics sufficient for high integration is provided by etching a second silicon layer of a SOI wafer to form a trench exposing a buried oxide film, forming a device isolation film filling the trench, wherein a silicide layer is formed at the side walls of the trench before filling the trench, thereby forming a silicide layer at the interface between a device isolation film in a device isolation region and a second silicon layer in an active region, and forming the transistor in the second silicon layer by subsequently using a salicide process.